The clock synchronization type serial data communication systems and the serial data communication methods have been used in various devices. In such a serial data communication, it is necessary for a data reception side (the slave device) to detect finish of reception of data. Prior instances 1 to 3 are now explained.
<First Prior Art>
FIG. 5 is a block diagram that shows a conventional structure of a serial data communication system, a reference number 12 in the figure shows a master device, a reference number 13 shows a slave device, a reference number 14 is a clock generating portion for generating clock signals CLK, a reference numeral 15 denotes a clock line for transmitting the clock signals CLK, and a reference numeral 16 denotes a data line for transmitting serial data TxD. In the system shown in the figure, the clock signals CLK are transmitted from the master device 12 to the slave device 13, and the serial data TxD are transmitted, synchronizing with the clock signals CLK. Such serial data TxD has STX (control code for text start) added before data body, data 1, data 2 and data 3, and ETX (control code for text finish) added after data body, data 1, data 2 and data 3, as shown in FIG. 6 such that the slave device 13 determines reception start and stores each data in a receive buffer (not shown) when recognizing STX, and determines reception prohibition and does command processing when recognizing ETX (see Japanese patent application publication No. H05-134736).
<Second Prior Art>
FIG. 7 is a block diagram which shows another instance of a conventional structure of a serial data communication system. In the system as shown in the figure, a handshake line 17 is provided in addition to the clock line 15 and the data line 16, and through the handshake line 17 a communication finish (that is, communication period) is notified to the slave device 13. An explanation of portions the same as FIG. 5 is not described by using the same reference numerals.
<Third Prior Art>
FIG. 8 is a block diagram that shows another alternate instance of a conventional structure of the serial data communication system. In such a system, a timer 18 is provided. Then, the timer 18 clocks from a point of time when the slave device 13 starts to receive the data (or from the point of time when receiving the last character data), and data receiving is compulsorily finished if no ETX is recognized after passing a predetermined time and an error processing is done (see Japanese patent application publication No. H10-200602). Similar to the above-mentioned, the explanation of portions the same as FIG. 5 is not described by using the same reference numerals.
In the past, the clock synchronization type serial data communication system and the serial data communication method have been used in various kinds of machines. A representative conventional structure of the communication system is now mentioned.
<Fourth Prior Art>
FIG. 13 is a block diagram that shows an instance of a conventional structure of the serial data communication system. In the figure, a reference numeral 112 denotes a master device, a reference numeral 113 denotes a slave device, a reference numeral 114 is a clock generating portion for generating clock signals, a reference numeral 115 denotes a data line for transmitting serial data TxD, and a reference numeral 117 denotes a clock line for transmitting clock signals CLK. In the system in the figure, the clock signals CLK are transmitted from the master device 112 to the slave device 113, and the serial data TxD are transmitted synchronizing with the clock signals CLK.
Various kinds of structures of the communication system in which the serial data can be also transmitted from the slave device 113 to the master device 112 in addition to the transmitting of serial data from the master device 112 to the slave device 113 have been proposed (see Japanese patent applications publication Nos. H06-243052 and 2003-163653).
<Fifth Prior Art>
FIG. 14 is a block diagram that shows another instance of the conventional structure of the serial data communication system. In the figure, a reference number 122 denotes a master device, a reference number 123 shows a slave device, a reference number 124 is a clock generating portion for generating clock signals, a reference numeral 125 denotes a data line for transmitting serial data TxD from the master device 122 to the slave device 123, a reference numeral 126 is a data line for transmitting serial data RxD from the slave device 123 to the master device 122, a reference numeral 127 denotes a clock line for transmitting clock signals CLK1 from the master device 122 to the slave device 123, and a reference numeral 128 denotes a handshake line. In the communication system shown in the figure, the master device 122 transmits the clock signal CLK1 for reception to the slave device 123 and the slave device 123 informs the master device 122 of a transmittable condition through the handshake line 128 at a timing when transmission of data is prepared. Receiving this, the master device 122 transmits the clock signal CLK1 for reception to the slave device 123. Then, the serial data RxD is transmitted from the slave device 123 to the master device 122, synchronizing with the clock signal CLK1.
<Sixth Prior Art>
FIG. 15 is a block diagram that shows another alternate instance of the conventional structure of the serial data communication system. An explanation of portions the same as FIG. 14 is not described by using the same reference numerals. In the communication system in the figure, the slave device 123 is provided with a clock generating portion 130 for generating the clock signal CLK2, and the clock signal CLK2 is transmitted from the slave device 123 to the master device 122 through a handshake line 131 (or a line dedicated for transmitting the clock signals). With such a structure, the serial data RxD is transmitted from the slave device 123 to the master device 122, synchronizing with the clock signal CLK2.